TC1796
System Units (Vol. 1 of 2)
Peripheral Control Processor (PCP)
User’s Manual 11-111 V2.0, 2007-07
PCP, V2.0
MINIT 1 –
7)
MSTEP.L 10 –
7)
MSTEP.U 10 –
7)
Jump
JL 4 – –
JC y = 4, n = 2 –
8)
JC.A y = 4, n = 2 –
8)
JC.I y = 4, n = 2 –
8)
JC.IA y = 4, n = 2 –
8)
DEBUG sdb - 0 = 2
sdb - 1 = exit_time
–
9)
1) The number of clock cycles for these instructions depends on several parameters such as the amount of data
to be copied, the type of memory, and the effective bus load.
2) f = Full Context save, s = Small Context save, m = Minimum Context save Time extended until any previous
ST.F instruction has completed.
3) Cycles = 5 internal + 3 minimum for FPI read (with 0 wait cycles + 1 cycle for bus arbitration)
4) Cycles = 4 internal + 4 minimum for FPI read/modify/write (with 0 wait cycles + 1 cycle bus arbitration)
5) Cycles = 2 internal + 3 minimum for FPI write (with 0 wait cycles + 1 cycle for bus arbitration)
Time starts after any previous ST.F instruction has completed.
6) 32/32 bit divide requires instruction DINIT + JC + 4 × DSTEP = 1 + 4(2) + 4 × 10 = 45 cycles
8/32 bit divide requires instruction RR + DINIT + JC + DSTEP = 1 + 1 + 4(2) + 10 = 16 cycles
7) 32 × 8 bit multiply requires instructions RR + MINIT + MSTEP.L = 1 + 1 + 10 = 12 cycles
32 × 16 bit multiply requires instructions 2 × RR + MINIT + 2 × MSTEP.L = 2 × 1 + 1 + 2 × 10 = 23 cycles
32 × 32 bit multiply requires instructions MINIT + 4 × MSTEP.U = 1 + 4 × 10 = 41 cycles
8) y = jump taken, n = jump not taken
9) sdb - 0 = Stop_on_Debug bit in instruction = 0 (disabling stop)
sdb - 1 = Stop_on_Debug bit in instruction = 1 (enabling stop)
exit_time = same time as for an exit instruction
Table 11-15 Instruction Timing (cont’d)
Instruction Number of Clock
Cycles
Comments Notes
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