Infineon Technologies TC1796 - Page 710

TC1796
System Units (Vol. 1 of 2)
Direct Memory Access Controller
User’s Manual 12-46 V2.0, 2007-07
DMA, V2.0
The OCDS Register describes the break capability of the DMA module. OCDSR is only
reset with the OCDS Reset.
DMA_OCDSR
DMA OCDS Register (064
H
) Reset Value: 0000 0000
H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
r
1514131211109876543210
0
BRL
1
BCHS1 BTRC1 0
BRL
0
BCHS0 BTRC0
r rw rw rw r rw rw rw
Field Bits Type Description
BTRC0 [1:0] rw Break Trigger Condition In Sub-Block 0
This bit field determines the transition type for the
transaction request bit TRSR.CH0x that leads to a
break condition in DMA Sub-Block 0.
00
B
No break condition is generated.
01
B
A break condition is generated when
TRSR.CH0x changes from 0 to 1.
10
B
A break condition is generated when
TRSR.CH0x changes from 1 to 0.
11
B
A break condition is generated when
TRSR.CH0x changes its state.
BCHS0 [4:2] rw Break Channel Select In Sub-Block 0
This bit field determines the DMA channel n of DMA
Sub-Block 0 whose transaction request bit
TRSR.CH0x is observed for signal transitions as
defined by BTRC0.
000
B
DMA channel 00 selected
001
B
DMA channel 01 selected
…
B
…
110
B
DMA channel 06 selected
111
B
DMA channel 07 selected