TC1796
System Units (Vol. 1 of 2)
Direct Memory Access Controller
User’s Manual 12-47 V2.0, 2007-07
DMA, V2.0
BRL0 5rwBreak On Request Lost in Sub-Block 0
This bit field determines whether a BREAK signal is
generated for DMA Sub-Block 0 when at least one of
its eight transaction lost interrupts becomes active.
0
B
No break condition is generated.
1
B
A break condition is generated for DMA Sub-
Block 0 when at least one of its eight
transaction lost interrupts becomes active.
BTRC1 [9:8] rw Break Trigger Condition In Sub-Block 1
This bit field determines the transition type for the
transaction request bit TRSR.CH1x that leads to a
break condition in DMA Sub-Block 1.
00
B
No break condition is generated.
01
B
A break condition is generated when
TRSR.CH1x changes from 0 to 1.
10
B
A break condition is generated when
TRSR.CH1x changes from 1 to 0.
11
B
A break condition is generated when
TRSR.CH1x changes its state.
BCHS1 [12:10] rw Break Channel Select In Sub-Block 1
This bit field determines the DMA channel n of DMA
Sub-Block 1 whose transaction request bit
TRSR.CH1x is observed for signal transitions as
defined by BTRC1.
000
B
DMA channel 10 selected
001
B
DMA channel 11 selected
...
B
...
110
B
DMA channel 16 selected
111
B
DMA channel 17 selected
BRL0 5rwBreak On Request Lost in Sub-Block 1
This bit field determines whether a BREAK signal is
generated for DMA Sub-Block 1 when at least one of
its eight transaction lost interrupts becomes active.
0
B
No break condition is generated.
1
B
A break condition is generated for DMA Sub-
Block 0 when at least one of its eight
transaction lost interrupts becomes active.
0 [7:6],
[31:14]
r Reserved
Read as 0; should be written with 0.
Field Bits Type Description
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