TC1796
System Units (Vol. 1 of 2)
Direct Memory Access Controller
User’s Manual 12-67 V2.0, 2007-07
DMA, V2.0
The bits in the Interrupt Clear Register make it possible to clear the channel interrupt
flags and the wrap buffer interrupt flags for DMA Channels mx.
WRPD1x
(x = 0-7)
24+x rh Wrap Destination Buffer for Channel 1x
These bits indicate which channels have done a
wrap-around of their destination buffer(s).
0
B
No wrap-around occurred for channel 1x.
1
B
A wrap-around occurred for channel 1x.
This bit is cleared by software by writing a 1 to
INTCR.CWRP1x or CHRSTR.CH1x.
DMA_INTCR
DMA Interrupt Clear Register (058
H
) Reset Value: 0000 0000
H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
C
WRP
17
C
WRP
16
C
WRP
15
C
WRP
14
C
WRP
13
C
WRP
12
C
WRP
11
C
WRP
10
C
WRP
07
C
WRP
06
C
WRP
05
C
WRP
04
C
WRP
03
C
WRP
02
C
WRP
01
C
WRP
00
wwwwwwwwwwwwwwww
1514131211109876543210
C
ICH
17
C
ICH
16
C
ICH
15
C
ICH
14
C
ICH
13
C
ICH
12
C
ICH
11
C
ICH
10
C
ICH
07
C
ICH
06
C
ICH
05
C
ICH
04
C
ICH
03
C
ICH
02
C
ICH
01
C
ICH
00
wwwwwwwwwwwwwwww
Field Bits Type Description
CICH0x
(x = 0-7)
xwClear Interrupt for DMA Channel 0x
These bits make it possible to clear the channel
interrupt flags INTSR.ICH0x and INTSR.IPM0x of
DMA channel 0x by software.
0
B
No action.
1
B
Bits INTSR.ICH0x and INTSR.IPM0x are
cleared.
Field Bits Type Description
To Next Page
Loading...