TC1796
System Units (Vol. 1 of 2)
Direct Memory Access Controller
User’s Manual 12-68 V2.0, 2007-07
DMA, V2.0
CICH1x
(x = 0-7)
8+x w Clear Interrupt for DMA Channel 1x
These bits make it possible to clear the channel
interrupt flags INTSR.ICH1x and INTSR.IPM1x of
DMA channel 1x by software.
0
B
No action.
1
B
Bits INTSR.ICH1x and INTSR.IPM1x are
cleared.
CWRP0x
(x = 0-7)
16+x w Clear Wrap Buffer Interrupt for DMA Channel 0x
These bits make it possible to clear the wrap source
buffer interrupt flag WRPSR.WRPS0x and the wrap
destination buffer interrupt flag WRPSR.WRPD0x
(both together) of DMA channel 0x by software.
0
B
No action.
1
B
Bits WRPSR.WRPS0x and WRPSR.WRPD0x
are cleared.
CWRP1x
(x = 0-7)
24+x w Clear Wrap Buffer Interrupt for DMA Channel 1x
These bits make it possible to clear the wrap source
buffer interrupt flag WRPSR.WRPS1x and the wrap
destination buffer interrupt flag WRPSR.WRPD1x
(both together) of DMA channel 1x by software.
0
B
No action.
1
B
Bits WRPSR.WRPS1x and WRPSR.WRPD1x
are cleared.
Field Bits Type Description
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