TC1796
System Units (Vol. 1 of 2)
Direct Memory Access Controller
User’s Manual 12-77 V2.0, 2007-07
DMA, V2.0
PRSEL [15:13] rw Peripheral Request Select
This bit field controls the hardware request input
multiplexer of DMA channel mx (m=0,1; see
Figure 12-6 on Page 12-10).
000
B
Input CHmx_REQI0 selected
001
B
Input CHmx_REQI1 selected
010
B
Input CHmx_REQI2 selected
011
B
Input CHmx_REQI3 selected
101
B
Input CHmx_REQI4 selected
110
B
Input CHmx_REQI5 selected
110
B
Input CHmx_REQI6 selected
111
B
Input CHmx_REQI7 selected
BLKM [18:16] rw Block Mode
BLKM determines the number of DMA moves executed
during one DMA transfer.
000
B
One DMA transfer has 1 DMA moves
001
B
One DMA transfer has 2 DMA moves
010
B
One DMA transfer has 4 DMA moves
011
B
One DMA transfer has 8 DMA moves
100
B
One DMA transfer has 16 DMA moves
others Reserved; do not use these combinations.
See also Figure 12-10 on Page 12-17.
RROAT 19 rw Reset Request Only After Transaction
RROAT determines whether or not the TRSR.CHmx
transfer request state flag is cleared after each transfer.
0
B
TRSR.CHmx is cleared after each transfer. A
transfer request is required for each transfer.
1
B
TRSR.CHmx is cleared when TCOUNT = 0 after
a transfer. One transfer request starts a complete
DMA transaction.
Field Bits Type Description
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