TC1796
System Units (Vol. 1 of 2)
Direct Memory Access Controller
User’s Manual 12-78 V2.0, 2007-07
DMA, V2.0
CHMODE 20 rw Channel Operation Mode
CHMODE determines the clear condition for control bit
TRSR.HTREmx of DMA channel mx.
0
B
Single Mode operation is selected for DMA
channel mx. After a transaction, DMA channel mx
is disabled for further hardware requests
(TRSR.HTREmx is cleared by hardware).
TRSR.HTREmx must be set again by software for
starting a new transaction.
1
B
Continuous Mode operation is selected for DMA
channel mx. After a transaction, bit
TRSR.HTREmx remains set.
CHDW [22:21] rw Channel Data Width
CHDW determines the data width for the read and write
moves of DMA channel mx.
00
B
8-bit (byte) data width for moves selected
01
B
16-bit (half-word) data width for moves selected
10
B
32-bit (word) data width for moves selected
11
B
Reserved
PATSEL [25:24] rw Pattern Select
This bit field selects the mode of the pattern detection
logic. Depending on the channel data width, PATSEL
selects different pattern detection configurations.
If pattern detection is enabled (PATSEL not equal 00
B
),
the pattern detection interrupt line will be activated an
the selected pattern match.
8-Bit channel data width (CHDW = 00
B
):
Selected pattern detection configuration; see
Table 12-2 on Page 12-4.
16-Bit channel data width (CHDW = 01
B
):
Selected pattern detection configuration; see
Table 12-3 on Page 12-5.
32-Bit channel data width (CHDW = 10
B
):
Selected pattern detection configuration; see
Table 12-4 on Page 12-8.
CHPRIO 28 rw Channel Priority
CHPRIO determines the priority of DMA channel mx for
the channel arbitration of Move Engine m.
0
B
DMA channel mx has a low channel priority.
1
B
DMA channel mx has a high channel priority.
Field Bits Type Description
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