Infineon Technologies TC1796 - Page 811

TC1796
System Units (Vol. 1 of 2)
LMB External Bus Unit
User’s Manual 13-33 V2.0, 2007-07
EBU, V2.0
The EBU uses the five region select outputs from the above scheme, in conjunction with
its own address decode logic, to react to PLMB accesses as follows:
1. Address is in the EBU register space:
An EBU register access is executed, and in case of a illegal register address, PLMB
Error Acknowledge is retuned.
2. Address matches exactly one enabled external region:
The requested access is performed to external memory.
3. Address matches more than one enabled region (overlapping regions):
The requested access is performed using the parameters from the region with
highest priority. The region with the lowest region number x (region 0) has the highest
priority. The emulator region has lowest priority).
4. Address matches disabled region(s) or no address match:
The EBU returns a PLMB Error Acknowledge.
Table 13-12 EBU Address Regions Size and Start Address Relations
MASK No. of Address
Bits compared
to BASE[26:12]
Range of Address
Bits compared to
BASE[26:12]
Region Size and
Start Address
Granularity
Range of Offset
Address Bits
within Region
1111
B
15 A[26:12] 4 Kbyte A[11:0]
1110
B
14 A[26:13] 8 Kbyte A[12:0]
1101
B
13 A[26:14] 16 Kbyte A[13:0]
1100
B
12 A[26:15] 32 Kbyte A[14:0]
1011
B
11 A[26:16] 64 Kbyte A[15:0]
1010
B
10 A[26:17] 128 Kbyte A[16:0]
1001
B
9 A[26:18] 256 Kbyte A[17:0]
1000
B
8 A[26:19] 512 Kbyte A[18:0]
0111
B
7 A[26:20] 1 Mbyte A[19:0]
0110
B
6 A[26:21] 2 Mbyte A[20:0]
0101
B
5 A[26:22] 4 Mbyte A[21:0]
0100
B
4 A[26:23] 8 Mbyte A[22:0]
0011
B
3 A[26:24] 16 Mbyte A[23:0]
0010
B
2 A[26:25] 32 Mbyte
1)
1) These region size selections do not affect the external address bus of the TC1796 because A24, A25,and A26
are not output at pins (only A[23:0] are available at TC1796 pins).
A[24:0]
0001
B
1 A[26] 64 Mbyte
1)
A[25:0]
0000
B
0 – 128 Mbyte
1)
A[26:0]