TC1796
System Units (Vol. 1 of 2)
LMB External Bus Unit
User’s Manual 13-87 V2.0, 2007-07
EBU, V2.0
EXTCLOCK [7:6] rw Frequency of External Clock at Pin BFCLKO
This bit field sets the frequency of pin BFCLKO for
accesses to both types of Burst Flash devices.
00
B
Equal to LMBCLK frequency. In the TC1796,
this selection is not allowed for LMBCLK (f
CPU
)
frequencies above 75 MHz.
01
B
1/2 of LMBCLK frequency.
10
B
1/3 of LMBCLK frequency.
11
B
1/4 of LMBCLK frequency (default after reset).
BFCMSEL 8rwBurst Flash Clock Mode Select
0
B
Clock signal is continuously available at pin
BFCLKO.
1
B
Clock signal is only available at pin BFCLKO
during a Burst Flash access (default after
reset). BFCLKO is at low level in inactive state.
EBSE0 9rwEarly Burst Signal Enable for Burst Flash Type 0
0
B
Outputs ADV and BAA are delayed by 1/2
LMBCLK clock period.
1
B
Output lines ADV and BAA are not delayed.
(see Page 13-73)
DBA0 10 rw Disable Burst Address Wrapping
0
B
The EBU automatically re-aligns any non-
aligned burst access to a Type 0 device so that
data can be fetched from the device in a single
burst transaction.
1
B
The EBU always starts any burst access to a
Type 0 device at the address specified by the
LMB request. Any required address wrapping
must be automatically provided by the Burst
Flash device.
Note: Care must be taken with the use of this feature.
The address at which wrapping should take
place varies with the LMB burst access size,
while Burst Flash devices wrap at fixed address
boundaries. Therefore, it is not possible to
guarantee correct behavior for all LMB
accesses when this bit is 1.
Field Bits Type Description
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