TC1796
System Units (Vol. 1 of 2)
LMB External Bus Unit
User’s Manual 13-88 V2.0, 2007-07
EBU, V2.0
FDBKEN 11 rw Burst Flash Clock Feedback Enable
0
B
BFCLK feedback not used. In this case, bit field
DTALTNCY must be set to 0000
B
.
1
B
Incoming data and control signals (from the
Burst Flash device) are re-synchronized to the
BFCLKI input.
DTALTNCY [15:12] rw Latency Cycle Control
This bit field determines the number of additional
LMBCLK cycles of latency to be used when sampling
inputs from the Burst Flash devices.
FETBLEN1 [19:16] rw Fetch Burst Length for Burst Flash Type 1
This bit field determines the maximum number of
burst data cycles which are executed by the EBU
during a Burst Flash Type 1 burst access.
000
B
1 data access (default after reset).
001
B
2 data accesses.
010
B
4 data accesses.
011
B
8 data accesses.
1XX
B
Reserved.
FBBMSEL1 20 rw Flash Burst Buffer Mode Select for Burst Flash
Type 1
0
B
Continuous mode.
1
B
Flash burst buffer length is defined by the value
of FETBLEN1 (default after reset).
WAITFUNC1 21 rw Function of WAIT input for Burst Flash Type 1
0
B
The WAIT input operates as a wait data bus
function on bursts (default after reset).
1
B
The WAIT input operates as a terminate burst
function.
EBSE1 25 rw Early Burst Signal Enable for Burst Flash Type 1
0
B
Outputs ADV and BAA are delayed by 1/2
LMBCLK period (default after reset).
1
B
Outputs ADV and BAA are not delayed.
(see Page 13-73)
Field Bits Type Description
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