Infineon Technologies TC1796 User Manual

TC1796
System Units (Vol. 1 of 2)
LMB External Bus Unit
User’s Manual 13-99 V2.0, 2007-07
EBU, V2.0
DATAC [15:14] rw Data Hold Cycles for Write Accesses
This bit field determines the basic number of Data
Hold phase clock cycles during write accesses. The
total number of Data Hold phase cycles further
depends on bit fields EBU_BUSCONx.CMULT and
EBU_BUSCONx.MULTMAP[4] (see also
Page 13-45).
00
B
No Data Hold Phase clock cycles available.
01
B
1 clock cycle selected.
10
B
2 clock cycles selected.
11
B
3 clock cycles selected.
BURSTC [18:16] rw Data Cycles during Burst Accesses
This bit field determines the basic number of data
cycles during burst accesses. The total number of
burst data cycles further depends on bit fields
EBU_BUSCONx.CMULT and
EBU_BUSCONx.MULTMAP[3] (see also
Page 13-46).
000
B
No burst data cycle selected.
001
B
1 clock cycle selected.
…
B
…
110
B
6 clock cycles selected.
111
B
7 clock cycles selected.
WAITWRC [21:19] rw Write Command Phase Cycles
This bit field determines the basic number of
Command Phase clock cycles during write accesses.
The total number of Command Phase clock cycles for
write accesses is defined by WAITWRC multiplied by
EBU_BUSCONx.CMULT (see also Page 13-43).
000
B
Reserved; do not use this combination.
001
B
1 clock cycle selected.
010
B
2 clock cycle selected.
…
B
…
111
B
7 clock cycle selected.
Field Bits Type Description

Infineon Technologies TC1796 Specifications

General

Brand	Infineon Technologies
Model	TC1796
Category	Controller
Language	English