Infineon Technologies TC1796 - Page 937

TC1796
System Units (Vol. 1 of 2)
System Timer
User’s Manual 15-20 V2.0, 2007-07
STM, V2.0
The bits in the STM Interrupt Set/Reset Register make it possible to set or clear the
compare match interrupt request status flags of register ICR.
Note: Reading register CMISRR always returns 0000 0000
H
.
STM_ISRR
STM Interrupt Set/Reset Register (40
H
) Reset Value: 0000 0000
H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
r
1514131211109876543210
0
CMP
1
IRS
CMP
1
IRR
CMP
0
IRS
CMP
0
IRR
r wwww
Field Bits Type Description
CMP0IRR 0wReset Compare Register CMP0 Interrupt Flag
0
B
Bit ICR.CMP0IR is not changed
1
B
Bit ICR.CMP0IR is cleared
CMP0IRS 1wSet Compare Register CMP0 Interrupt Flag
0
B
Bit ICR.CMP0IR is not changed
1
B
Bit ICR.CMP0IR is set. The state of bit CMP0IRR
is “don’t care” in this case
CMP1IRR 2wReset Compare Register CMP1 Interrupt Flag
0
B
Bit ICR.CMP0IR is not changed
1
B
Bit ICR.CMP0IR is cleared
CMP1IRS 3wSet Compare Register CMP1 Interrupt Flag
0
B
Bit ICR.CMP1IR is not changed
1
B
Bit ICR.CMP1IR is set. The state of bit CMP1IRR
is “don’t care” in this case
0 [31:4] r Reserved
Read as 0; should be written with 0.