TC1796
System Units (Vol. 1 of 2)
System Timer
User’s Manual 15-21 V2.0, 2007-07
STM, V2.0
In the TC1796, the compare match interrupt output signals of the STM, STMIR0 and
STMIR1, are controlled by the STM Service Request Control Registers STM_SRC0 and
STM_SRC1.
Note: Further details of interrupt handling and processing are described in Chapter 14
of this TC1796 System Units (Vol. 1 of 2) User’s Manual
STM_SRC0
STM Service Request Control Register 0
(FC
H
) Reset Value: 0000 0000
H
STM_SRC1
STM Service Request Control Register 1
(F8
H
) Reset Value: 0000 0000
H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
r
1514131211109876543210
SET
R
CLR
R
SRR SRE 0 TOS 0 SRPN
w w rh rw r rw r rw
Field Bits Type Description
SRPN [7:0] rw Service Request Priority Number
TOS 10 rw Type of Service Control
SRE 12 rw Service Request Enable
SRR 13 rh Service Request Flag
CLRR 14 w Request Clear Bit
SETR 15 w Request Set Bit
0 [9:8], 11,
[31:16]
r Reserved
Read as 0; should be written with 0.
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