TC1796
System Units (Vol. 1 of 2)
Watchdog Timer
User’s Manual 16-19 V2.0, 2007-07
WDT, V2.0
Time-out Period After Reset
After reset, the initial count value for the timer is fixed at FFFC
H
when the WDT clock
starts running. The WDT counts up at a rate determined by WDT_SR.WDTIS, which is
0 after any reset (f
SYS
/16384). Counting up from FFFC
H
, it takes four clocks for the
counter to overflow, so the Time-out Period defaults to a period of 4 × 16384/f
SYS
=
65536/f
SYS
. This establishes the real-time deadline for software to initialize the Watchdog
and critical system registers, and to then set ENDINIT. For example, the Time-out Period
after reset would correspond to 1.6 ms (@ 40 MHz system frequency).
Changing the input frequency selection via WDT_CON1.WDTIR during this initial Time-
out Period has no immediate effect, because frequency selection is actually determined
by WDT_SR.WDTIS, but WDT_CON1.WDTIR is only copied into WDT_SR.WDTIS after
WDT_CON0.ENDINIT has been set to 1, that is, after Time-Out Mode has been properly
exited. Hence, the new input frequency will become effective only in a subsequent Time-
out Period.
Time-out Period During Normal Operation
As after reset, the WDT counter is initially set to FFFC
H
when Time-Out Mode is entered,
and Time-Out Mode expires when the counter overflows. However, there are two
differences to the Time-out Period after reset. First, the input frequency can be either
f
SYS
/256 or f
SYS
/16384, depending on the programmed state of bit WDT_SR.WDTIS
before the Time-out Period was entered. Second, because there is no synchronization
of the clock divider to the mode transitions of the Watchdog, the next clock pulse,
incrementing the counter to FFFD
H
, may come after one clock divider period, or
immediately after the counter was initially set to FFFC
H
. Thus, the minimum duration of
the Time-out Period in the latter case will only be three counter clocks. The possible
minimum and maximum periods are given in Table 16-8.
The WDT input clock rate can not be changed during the Time-out Period. The control
bit for the input clock rate, WDT_SR.WDTIS, is loaded from WDT_CON1.WDTIR when
WDT_CON0.ENDINIT is set to 1, that is, after Time-Out Mode has been properly exited.
Hence, the new input frequency will become effective only in the subsequent Time-out
Period.
Table 16-8 Time-out Period During Normal Operation
WDTIS Min./Max. Period Example
@ f
SYS
= 75 MHz
0min.3× 16384/f
SYS
= 49152/f
SYS
0.66 ms
max. 4 × 16384/f
SYS
= 65536/f
SYS
0.87 ms
1min.3× 256/f
SYS
= 768/f
SYS
10.2 µs
max. 4 × 256/f
SYS
= 1024/f
SYS
13.7 µs
To Next Page
Loading...