TC1796
System Units (Vol. 1 of 2)
Watchdog Timer
User’s Manual 16-33 V2.0, 2007-07
WDT, V2.0
WDTOE 1rhWatchdog Overflow Error Status Flag
0
B
No Watchdog overflow error.
1
B
A Watchdog overflow error has occurred.
This bit is set by hardware when the WDT overflows
from FFFF
H
to 0000
H
. This bit is only cleared when:
• A power-on, hardware, or software reset occurs;
• WDT_CON0.ENDINIT is set to 1 during a Valid
Modify Access.
However, it is not possible to cleared this bit if the
WDT is in Prewarning Mode, indicated by
WDT_SR.WDTPR = 1.
WDTIS 2rhWatchdog Input Clock Status Flag
0
B
WDT input clock is f
SYS
/16384
(default after reset).
1
B
WDT input clock is f
SYS
/256.
This bit is updated with the state of bit
WDT_CON1.WDTIR after WDT_CON0.ENDINIT is
written with 1 during a Valid Modify Access to register
WDT_CON0.
WDTDS 3rhWatchdog Enable/Disable Status Flag
0
B
WDT is enabled (default after reset).
1
B
WDT is disabled.
This bit is updated with the state of bit
WDT_CON1.WDTDR after WDT_CON0.ENDINIT is
written with 1 during a Valid Modify Access to register
WDT_CON0.
WDTTO 4rhWatchdog Time-Out Mode Flag
0
B
Normal mode.
1
B
The Watchdog is operating in Time-Out Mode
(default after reset).
This bit is set to 1 when Time-Out Mode is entered,
automatically after a reset and after every Password
Access to register WDT_CON0. It is automatically
cleared by hardware when Time-Out Mode is properly
terminated through a Valid Modify Access to
WDT_CON0. It is left set when a Watchdog error
occurs during Time-Out Mode, and Prewarning Mode
is entered.
Field Bits Type Description
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