TC1796
System Units (Vol. 1 of 2)
On-Chip Debug Support
User’s Manual 17-3 V2.0, 2007-07
OCDS, V2.0
• OCDS Level 1 module of PCP
• OCDS Level 2 interface of PCP
• OCDS Level 1 module in the BCU of the System Peripheral Bus (SBCU)
• OCDS Level 1 module in the BCU of the Remote Peripheral Bus (RBCU)
• OCDS Level 1 facilities within the DMA controller
• OCDS Level 2 interface of the DMA controller
• Cerberus - OCDS System Control Unit (OSCU)
• Cerberus - Multi-Core Break Switch (MCBS)
• Cerberus - JTAG Debug Interface (JDI)
• Suspend functionality of the peripherals at the System Peripheral Bus and Remote
Peripheral Bus
Summary of OCDS Features
• TriCore Level 1 OCDS:
– Hardware event generation
– Break by DEBUG instruction or Break signal from break switch
– Full hardware supported single step
– Software Single-Step (code patching) also possible
– Concurrent access to memory and SFRs via Cerberus possible
• PCP Level 1 OCDS:
– Break by DEBUG instruction or Break signal from break switch
– Concurrent access to memory and SFRs via Cerberus possible
• DMA Level 1 OCDS:
– Break request on error
– Event generation on specified channel activity
– Suspending pre-selected channels
• BCU Level 1 OCDS:
– Event generation on specified transactions
• 16-pin Level 2 trace port; outputs either TriCore, PCP or DMA trace
• OCDS System Control Unit (Cerberus OSCU):
– Extensive control using only a minimum number of pins (no pins apart from JTAG)
– Connecting a debugger to a running system allowed (hot attach)
– Built in System security
– Optional halt after reset
– Debug resources not affected by system reset
• Multi-Core Break Switch (Cerberus MCBS):
– TriCore, PCP, DMA, break pins and BCUs available as break sources
– TriCore and PCP available as break targets; other parts can be suspended in
addition
– Synchronous stop and restart of the system
– Break to Suspend converter
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