N2HET Control Registers
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SPNU563A–March 2018
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High-End Timer (N2HET) Module
23.4.13 HR Share Control Register (HETHRSH)
N2HET1: offset = FFF7 B834h; N2HET2: offset = FFF7 B934h
Figure 23-68. HR Share Control Register (HETHRSH)
31 16
Reserved
R-0
15 14 13 12 11 10 9 8
HR
SHARE31/30
HR
SHARE29/28
HR
SHARE27/26
HR
SHARE25/24
HR
SHARE23/22
HR
SHARE21/20
HR
SHARE19/18
HR
SHARE17/16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7 6 5 4 3 2 1 0
HR
SHARE15/14
HR
SHARE13/12
HR
SHARE11/10
HR
SHARE9/8
HR
SHARE7/6
HR
SHARE5/4
HR
SHARE3/2
HR
SHARE1/0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 23-29. HR Share Control Register (HETHRSH) Field Descriptions
Bit Field Value Description
31-16 Reserved 0 Reads return 0. Writes have no effect.
15-0 HRSHARE
n+1 / n
HR Share Bits
Enables the share of the same pin for two HR structures. For example, if bit HRSHARE1/0 is set,
the pin HET[0] will then be connected to both HR input structures 0 and 1.
Note: If HR share bits are used, pins not connected to HR structures (the odd number pin in each
pair) can be accessed as general inputs/outputs.
0 HR Input of HET[n+1] and HET[n] are not shared.
1 HR Input of HET[n+1] and HET[n] are shared; both measure pin HET[n].
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