PMM Operation
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SPNU563A–March 2018
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Power Management Module (PMM)
5.3.4.2 Turning a Power Domain On
A power domain can be turned on by writing the correct key to the LOGICPDON register. PMM will
automatically restart the clocks to the power domain once the Active power state is restored if the
“automatic clock enable upon wake up” option is selected. If this option is not selected, the application can
turn on clocks to the power domain by clearing the PDCLK_DIS register manually. The application must
poll the DOMAINISON register to ensure that the power has been fully restored before enabling the
clocks.
5.3.5 Reset Management
PMM handles the reset sequence for each power domain. When a power domain is turned on from an off
state, the PMM will reset the power domain to ensure that all logic begins in its default reset state.
PMM generates nPORRST (power-on reset), nRST (system reset), nPRST (peripheral reset), and nTRST
(test / debug logic reset) for each domain.
5.3.6 Diagnostic Power State Controller (PSCON)
Each power domain state is controlled by a primary PSCON. There is a second PSCON as well for each
power domain. This is the diagnostic PSCON. All power management inputs to a power domain are
controlled only by the primary PSCON. All power management outputs from the power domain are fed
back to both the primary and the diagnostic PSCON.
The PMM commands both the PSCON identically so that they are always in a lock-step operating mode. A
dedicated compare unit checks the outputs of the two PSCON modules on every cycle.
5.3.7 PSCON Compare Block
The diagnostic compare block can operate in one of four modes.
5.3.7.1 Lock-Step Mode
This is the default mode of operation of the PSCON compare block. The PSCON diagnostic compare
block compares the outputs from the two PSCONs on every cycle. Any mismatch in the PSCON outputs is
indicated as a PSCON compare error. This error signal is mapped to the Error Signaling Module’s (ESM)
Group1 channel 38. The application can define the response to this error.
5.3.7.2 Self-Test Mode
A self-test mechanism is provided to check the PSCON compare logic for faults. The compare error signal
output is disabled in self-test mode. The PSCON diagnostic compare block generates two types of
patterns during self-test mode: compare match test followed by compare mismatch test. During the self-
test, each test pattern is applied on both PSCON signal ports of the PSCON diagnostic compare block
and then is clocked for one cycle. The duration of the self-test is 24 cycles. Any detected fault is indicated
as a self-test error, mapped to ESM group1 channel 39. If no fault is detected, the self-test complete flag
is set.
The application can poll for this flag to be set and then switch the mode of the PSCON compare block
back to lock-step mode by writing to the mode key register.
NOTE: PSCON operation when compare block is in self-test mode
When the PSCON compare block is in its self-test mode, both PSCONs continue to function
normally. However, there is no comparison done on the PSCON outputs.
Compare match test:
An identical vector is applied to both input ports at the same time, thereby expecting a compare match. If
the compare unit produces a mismatch then the self-test error flag is set and the self-test error signal is
generated. The compare match test is terminated if a compare mismatch is detected. The compare match
test takes 4 cycles to complete when the test passes.
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