ADC Registers
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SPNU563A–March 2018
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Analog To Digital Converter (ADC) Module
22.3.76 ADC Group2 Current Count Register (ADG2CURRCOUNT)
Figure 22-107 and Table 22-82 describe the ADG2CURRCOUNT register.
Figure 22-107. ADC Group2 Current Count Register (ADG2CURRCOUNT) (offset = 1ACh)
31 5 4 0
Reserved G2_CURRENT_COUNT
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22-82. ADC Group2 Current Count Register (ADG2CURRCOUNT) Field Descriptions
Bit Field Value Description
31-5 Reserved 0 Reads return 0. Writes have no effect.
4-0 G2_CURRENT_
COUNT
CURRENT_COUNT value for the Group2 conversions when enhanced channel selection mode is
enabled. Refer to Section 22.2.2.2.2 for a description of the enhanced channel selection mode.
This register resets to 0 on any of the following conditions:
• A peripheral reset occurs
• An ADC software reset occurs via the ADC Reset Control Register (ADRSTCR)
• G2_CURRENT_COUNT becomes equal to G2_MAX_COUNT
• Application writes zeros to ADG2CURRCOUNT register
• Group2's result RAM is reset
A read from the ADG2CURRCOUNT register returns the value of the current index into the
Group2's look-up table.
22.3.77 ADC Group2 Maximum Count Register (ADG2MAXCOUNT)
Figure 22-108 and Table 22-83 describe the ADG2MAXCOUNT register.
Figure 22-108. ADC Group2 Maximum Count Register (ADG2MAXCOUNT) (offset = 1B0h)
31 5 4 0
Reserved G2_MAX_COUNT
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22-83. ADC Group2 Maximum Count Register (ADG2MAXCOUNT) Field Descriptions
Bit Field Value Description
31-5 Reserved 0 Reads return 0. Writes have no effect.
4-0 G2_MAX_
COUNT
MAX_COUNT value for the Group2 conversions when enhanced channel selection mode is
enabled. Refer to Section 22.2.2.2.2 for a description of the enhanced channel selection mode.
It is recommended to clear the Group2's CURRENT_COUNT register (ADG2CURRCOUNT)
whenever the G2_MAX_COUNT is changed.
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