Texas Instruments TMS570LC4357

ESM Control Registers www.ti.com
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SPNU563A–March 2018
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Error Signaling Module (ESM)
16.4.26 ESM Interrupt Enable Set/Status Register 7 (ESMIESR7)
This register is dedicated for Group1 Channel[95:64].
Figure 16-36. ESM Interrupt Enable Set/Status Register 7 (ESMIESR7) [offset = 88h]
31 16
INTENSET[95:80]
R/WP-0
15 0
INTENSET[79:64]
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 16-28. ESM Interrupt Enable Set/Status Register 7 (ESMIESR7) Field Descriptions
Bit Field Value Description
95-64 INTENSET Set interrupt enable.
Read in User and Privileged mode. Write in Privileged mode only.
0 Read: Interrupt is disabled.
Write: Leaves the bit and the corresponding clear bit in the ESMIECR7 register unchanged.
1 Read: Interrupt is enabled.
Write: Enables interrupt and sets the corresponding clear bit in the ESMIECR7 register.
16.4.27 ESM Interrupt Enable Clear/Status Register 7 (ESMIECR7)
This register is dedicated for Group1 Channel[95:64].
Figure 16-37. ESM Interrupt Enable Clear/Status Register 7 (ESMIECR7) [offset = 8Ch]
31 16
INTENCLR[95:80]
R/WP-0
15 0
INTENCLR[79:64]
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 16-29. ESM Interrupt Enable Clear/Status Register 7 (ESMIECR7) Field Descriptions
Bit Field Value Description
95-64 INTENCLR Clear interrupt enable.
Read in User and Privileged mode. Write in Privileged mode only.
0 Read: Interrupt is disabled.
Write: Leaves the bit and the corresponding clear bit in the ESMIESR7 register unchanged.
1 Read: Interrupt is enabled.
Write: Disables interrupt and clears the corresponding clear bit in the ESMIESR7 register.