VIM Interrupt
Vector Table 1
VIM
Core1
VIM
Core2
To CPU1
To CPU2
VIM Interrupt
Vector Table 2
MMR I/F1
INT_REQ
CCM
2 cyc
delay
2 cyc
delay
2 cyc
delay
Dual VIM for Safety
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SPNU563A–March 2018
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Vectored Interrupt Manager (VIM) Module
19.2 Dual VIM for Safety
A block diagram of Dual VIM for safety support is shown in Figure 19-1. To reduce probability of common
cause failure, the VIM module mimics the dual CPU scheme of two cycle delayed operation of the two
cores. In this case, the MMR (Memory Mapped Register) interface to the second instance is delayed by
two cycles. Similarly, the interrupt inputs are also delayed by two cycles to the second instance.
A separate set of “2 cycle” delayed versions of output ports for the CPU interrupt interface of the VIM1 are
provided. These will be used as one of the compare inputs of CPU Compare Module (CCM). The CPU
interface signals of VIM2 are used as second set of inputs of CCM.
VIM2 uses the same address space as that of VIM1. During LockStep mode, any write to VIM1 (including
the Interrupt Vector Table) will be routed to VIM2 as well so that the secondary instance is programmed
exactly as the first one and provide compare diagnostic support. Auto initialization of the VIM1 Interrupt
Vector Table will result in VIM2 Interrupt Vector Table getting initialized as well in this mode. In this mode,
reads from VIM will return only VIM1 data.VIM2 registers and Interrupt Vector Table cannot be read out in
Locked mode.
Figure 19-1. Block Diagram of Dual VIM for Safety Support
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