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Module Operation
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SPNU563A–March 2018
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System Memory Protection Unit (NMPU)
11.2 Module Operation
11.2.1 Functional Mode
On reset, NMPU is disabled and no filtering will be done on the bus. User must ensure that no bus
transaction from the master is on going while NMPU is getting disabled or enabled. This is similar to the
need to flush transactions using memory barrier instructions on the CPU before changing CPU MPU
setting.
The MPU can be enabled by writing 0xAh to the MPUENA key bits of MPUCTRL1 register and can be
disabled by writing 0x5h to the same bits.
Access permission (AP) for each MPU region is defined in AP field in the MPU region access control
register (MPUREGACR), see Table 11-2.
Table 11-2. Access Permission
AP Field Privilege Mode Permissions User Mode Permissions
000 No Access No Access
001 Read/Write No Access
010 Read/Write Read Only
011 Read/Write Read/Write
100 No Access No Access
101 Read only No Access
110 Read only Read only
111 No Access No Access
Each MPU region has three control registers:
• MPUREGBASE: MPU based address register. It defines the base address for a particular MPU region
• MPUREGSENA: MPU region size and enable register. It defines the size of a particular MPU region
and allows you to enable the region
• MPUREGACR: MPU region access control register. It defines the MPU region accessing permission
for user or privilege mode
NMPU has one region register that you have to configure to determine which MPU region user is
programming the corresponding MPUREGBASE, MPUREGSENA, and MPUREGACR registers. In this
scheme, the MPUREGBASE, MPUREGSENA, and MPUREGACR can share the same memory map
offset from user programming point of view.
Size of each MPU region can vary from 32 bytes to 4 GB. Region based address must start at an offset
that is a multiple of region size. In case the base address does not start at an offset that is a multiple of
region size, the region size takes priority and MPU ignores the LSB bits of base address.
Overlapping regions enable efficient programming of memory map. When the incoming address hits
multiple MPU regions, access permission is decided by the highest numbered region for which there was
an address compare match. In MPU configuration with 8 regions, region 0 has the lowest priority and
region 7 has the highest priority.
Figure 11-2 shows how the region priority is resolved in a high-level abstraction.
MPU does not support default background memory map. If memory protection is enabled without region
configuration, all transactions will result in bus error response. Before the protection unit is enabled, care
needs to be taken to ensure that at least one valid protection region is specified and its access permission
fields are defined.
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