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Safety Features
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SPNU563A–March 2018
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I/O Multiplexing and Control Module (IOMM)
6.6 Safety Features
The IOMM supports certain safety functions that are designed to prevent unintentional changes to the I/O
multiplexing configuration. These are described in the following sections.
6.6.1 Locking Mechanism for Memory-Mapped Registers
The IOMM contains a mechanism to prevent any spurious writes from changing any of the PINMMR
values. The PINMMRs are locked by default and after any system reset. None of the IOMM registers can
be written under this condition. The application can read any of the IOMM registers regardless of the state
of the locking mechanism.
• Enabling Write Access to the PINMMRs
To enable write access to the PINMMRs, the CPU must write 0x83e70b13 to the kick0 register followed by
a write of 0x95a4f1e0 to the kick1 register.
• Disabling Write Access to the PINMMRs
It is recommended to disable write access to the PINMMRs once the I/O multiplexing configuration is
completed. This can be done by:
• writing any other data value to either of the kick registers, or
• restarting the unlock sequence by writing 0x83e70b13 to the kick0 register
NOTE: No Error On Write to Locked PINMMRs
There is no error response on any write accesses to the PINMMRs when write access is
disabled. None of the PINMMRs change state due to this write.
6.6.2 Error Conditions
The IOMM generates one error signal that is mapped to the Error Signaling Module’s Group 1,
channel 37. This error signal is generated under either of the following two conditions:
• Address Error – occurs when there is a read or a write access to an un-implemented memory location
within the IOMM register frame.
• Protection Error – occurs when the CPU writes to an IOMM register while not in a privileged mode of
operation.
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