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EPC Control Registers
491
SPNU563A–March 2018
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Error Profiling Controller (EPC)
12.4.3 Uncorrectable Error Status Register (UERRSTAT)
Figure 12-4. Uncorrectable Error Status Register (UERRSTAT) (offset = 08h)
31 16
Reserved
R-0
15 2 1 0
Reserved UE1 UE0
R-0 R/W1CP-0 R/W1CP-0
LEGEND: R/W = Read/Write; R = Read only; W1CP = Write 1 to clear in privilege mode only; -n = value after asynchronous reset by
power-on reset
Table 12-4. Uncorrectable Error Status Register (UERRSTAT) Field Descriptions
Bit Field Value Description
31-2 Reserved 0 Reserved. Reads return 0.
1-0 UEn Uncorrectable ECC Fault Status Bit for interface n. Each bit corresponds to one uncorrectable EPC-IP
interface. If the IP triggers uncorrectable error, one of these bits gets set. Once it is set, it can only be
cleared by power-on reset or CPU write-clear in privilege mode or by reading the corresponding
UERRADDR register. Any of these bits set causes an uncorrectable error event (uerr_event) to be
triggered to ESM.
The number of implemented bits depends on the number of implemented EPC IP uncorrectable address
ports. Unimplemented bits are reserved and are not writable. Reserved bits are read as 0.
Read:
0 Uncorrectable ECC fault status bit is not active for interface n.
1 Uncorrectable ECC fault status bit is active for interface n.
Write in Privilege:
0 No effect.
1 Clear this flag bit.
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