How to Use SCM
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SPNU563A–March 2018
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SCR Control Module (SCM)
3.3.2 How to Initiate Self-test Sequence
It is necessary to be able to do self-test of the interconnect hardware checker logic to detect residual faults
when you decide at appropriate time in the application control loop. The self-test logic will create normal
and erroneous transaction from each master to each slave according to the bus connection matrix to verify
that the hardware checker and the interconnect functioning properly.
To initiate the self-test sequence, you should switch to privilege mode.
1. Software needs to ensure that MASK_SOFT_RESET control bit of the interconnect self-test control
register (Interconnect SDC MMR offset at 0xFA00_0000[0]) is 0.
2. Software needs to ensure that GCLK1 is still running.
3. Software needs to ensure that all bus master connecting to interconnect should stop sending new
transaction to interconnect. The hardware will make sure that all outstanding transaction will complete.
4. Software writes to SCM control register bit field DTC_SOFT_RESET a key value: 0xA to initiate self-
test.
5. CPU0 and CPU1 must execute WFI instruction.
a. At this point, the hardware will ensure that there is no outstanding transaction inside interconnect
and will trigger self-test.
b. While hardware checker self-test is ongoing, the CPU will be held in reset and released until self-
test completes
6. Once self-test completes, CPU will boot up from 0x0 again and you need to read interconnect
diagnostic register to inspect for any error detected during self-test. Refer to device technical reference
manual for base address.
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