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System and Peripheral Control Registers
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SPNU563A–March 2018
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Architecture
2.5.3 Peripheral Central Resource (PCR) Control Registers
This section describes the Peripheral Central Resource (PCR) control registers. The are three PCRx in
this microcontroller. The start address of the PCR1 register frame is FFFF 1000h. The start address of the
PCR2 register frame is FCFF 1000h. The start address of the PCR3 register frame is FFF7 8000h.
Table 2-85 lists the registers in the PCR, which are used to configure the following main functionalities:
• Protection control to the peripherals in PCS (Peripheral Memory) and PS (Peripheral) regions.
• Powerdown control to the peripherals in PCS (Peripheral Memory) and PS (Peripheral) regions.
• Powerdown control to the CoreSight debug peripherals in debug frame region from FFA0 0000h to
FFAF FFFFh.
• Master-ID Filtering control to the peripherals in PS (Peripheral), PPS (Privileged Peripheral) , PPSE
(Privileged Peripheral Extended) regions.
• Master-ID Filtering control to the peripheral memories in PCS (Peripheral Memory), and PPCS
(Privileged Peripheral Memory) regions.
The following sections provide detailed information about these registers. Not all chip selects exist on this
device.
Table 2-85. Peripheral Central Resource Control Registers
Offset Acronym Register Description Section
00h PMPROTSET0 Peripheral Memory Protection Set Register 0 Section 2.5.3.1
04h PMPROTSET1 Peripheral Memory Protection Set Register 1 Section 2.5.3.2
10h PMPROTCLR0 Peripheral Memory Protection Clear Register 0 Section 2.5.3.3
14h PMPROTCLR1 Peripheral Memory Protection Clear Register 1 Section 2.5.3.4
20h PPROTSET0 Peripheral Protection Set Register 0 Section 2.5.3.5
24h PPROTSET1 Peripheral Protection Set Register 1 Section 2.5.3.6
28h PPROTSET2 Peripheral Protection Set Register 2 Section 2.5.3.7
2Ch PPROTSET3 Peripheral Protection Set Register 3 Section 2.5.3.8
40h PPROTCLR0 Peripheral Protection Clear Register 0 Section 2.5.3.9
44h PPROTCLR1 Peripheral Protection Clear Register 1 Section 2.5.3.10
48h PPROTCLR2 Peripheral Protection Clear Register 2 Section 2.5.3.11
4Ch PPROTCLR3 Peripheral Protection Clear Register 3 Section 2.5.3.12
60h PCSPWRDWNSET0 Peripheral Memory Power-Down Set Register 0 Section 2.5.3.13
64h PCSPWRDWNSET1 Peripheral Memory Power-Down Set Register 1 Section 2.5.3.14
70h PCSPWRDWNCLR0 Peripheral Memory Power-Down Clear Register 0 Section 2.5.3.15
74h PCSPWRDWNCLR1 Peripheral Memory Power-Down Clear Register 1 Section 2.5.3.16
80h PSPWRDWNSET0 Peripheral Power-Down Set Register 0 Section 2.5.3.17
84h PSPWRDWNSET1 Peripheral Power-Down Set Register 1 Section 2.5.3.18
88h PSPWRDWNSET2 Peripheral Power-Down Set Register 2 Section 2.5.3.19
8Ch PSPWRDWNSET3 Peripheral Power-Down Set Register 3 Section 2.5.3.20
A0h PSPWRDWNCLR0 Peripheral Power-Down Clear Register 0 Section 2.5.3.21
A4h PSPWRDWNCLR1 Peripheral Power-Down Clear Register 1 Section 2.5.3.22
A8h PSPWRDWNCLR2 Peripheral Power-Down Clear Register 2 Section 2.5.3.23
ACh PSPWRDWNCLR3 Peripheral Power-Down Clear Register 3 Section 2.5.3.24
C0h PDPWRDWNSET Debug Frame Power-Down Set Register Section 2.5.3.25
C4h PDPWRDWNCLR Debug Frame Power-Down Clear Register Section 2.5.3.26
200h MSTIDWRENA MasterID Protection Write Enable Register Section 2.5.3.27
204h MSTIDENA MasterID Protection Enable Register Section 2.5.3.28
208h MSTIDDIAGCTRL MasterID Diagnostic Control Register Section 2.5.3.29
300h PS0MSTID_L Peripheral Frame 0 Master-ID Protection Register_L Section 2.5.3.30
304h PS0MSTID_H Peripheral Frame 0 Master-ID Protection Register_H Section 2.5.3.31
308h PS1MSTID_L Peripheral Frame 1 Master-ID Protection Register_L Section 2.5.3.32
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