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Control Registers and Control Packets
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SPNU563A–March 2018
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Direct Memory Access Controller (DMA) Module
20.3 Control Registers and Control Packets
The DMA control registers are summarized in Table 20-7. The base address for the control registers is
FFFF F000h. The control packets are summarized in Table 20-8. The base address for the control
packets is FFF8 0000h. Each register begins on a word boundary. All registers and control packets are
accessible in 8, 16, and 32 bit.
NOTE: The register definitions are given for a full DMA module configuration (32 channels, 64
requests, 2 Ports, Dual CPU support). Writes and Reads of bits pertaining to features not
included in the DMA implementation as defined in the device-specific data manual are
possible without error; however, they will have no affect on device operation.
Table 20-7. DMA Control Registers
Offset Acronym Register Description Section
00h GCTRL Global Control Register Section 20.3.1.1
04h PEND Channel Pending Register Section 20.3.1.2
0Ch DMASTAT DMA Status Register Section 20.3.1.3
10h DMAREVID DMA revision ID Register Section 20.3.1.4
14h HWCHENAS HW Channel Enable Set and Status Register Section 20.3.1.4
1Ch HWCHENAR HW Channel Enable Reset and Status Register Section 20.3.1.6
24h SWCHENAS SW Channel Enable Set and Status Register Section 20.3.1.7
2Ch SWCHENAR SW Channel Enable Reset and Status Register Section 20.3.1.8
34h CHPRIOS Channel Priority Set Register Section 20.3.1.9
3Ch CHPRIOR Channel Priority Reset Register Section 20.3.1.10
44h GCHIENAS Global Channel Interrupt Enable Set Register Section 20.3.1.11
4Ch GCHIENAR Global Channel Interrupt Enable Reset Register Section 20.3.1.12
54h DREQASI0 DMA Request Assignment Register 0 Section 20.3.1.13
58h DREQASI1 DMA Request Assignment Register 1 Section 20.3.1.14
5Ch DREQASI2 DMA Request Assignment Register 2 Section 20.3.1.15
60h DREQASI3 DMA Request Assignment Register 3 Section 20.3.1.16
64h DREQASI4 DMA Request Assignment Register 4 Section 20.3.1.13
68h DREQASI5 DMA Request Assignment Register 5 Section 20.3.1.13
6ch DREQASI6 DMA Request Assignment Register 6 Section 20.3.1.13
70h DREQASI7 DMA Request Assignment Register 7 Section 20.3.1.13
94h PAR0 Port Assignment Register 0 Section 20.3.1.21
98h PAR1 Port Assignment Register 1 Section 20.3.1.22
9Ch PAR2 Port Assignment Register 2 Section 20.3.1.23
A0h PAR3 Port Assignment Register 3 Section 20.3.1.24
B4h FTCMAP FTC Interrupt Mapping Register Section 20.3.1.25
BCh LFSMAP LFS Interrupt Mapping Register Section 20.3.1.26
C4h HBCMAP HBC Interrupt Mapping Register Section 20.3.1.27
CCh BTCMAP BTC Interrupt Mapping Register Section 20.3.1.28
DCh FTCINTENAS FTC Interrupt Enable Set Register Section 20.3.1.29
E4h FTCINTENAR FTC Interrupt Enable Reset Register Section 20.3.1.30
ECh LFSINTENAS LFS Interrupt Enable Set Register Section 20.3.1.31
F4h LFSINTENAR LFS Interrupt Enable Reset Register Section 20.3.1.32
FCh HBCINTENAS HBC Interrupt Enable Set Register Section 20.3.1.33
104h HBCINTENAR HBC Interrupt Enable Reset Register Section 20.3.1.34
10Ch BTCINTENAS BTC Interrupt Enable Set Register Section 20.3.1.35
114h BTCINTENAR BTC Interrupt Enable Reset Register Section 20.3.1.36
11Ch GINTFLAG Global Interrupt Flag Register Section 20.3.1.37
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