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Control Registers and Control Packets
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SPNU563A–March 2018
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Direct Memory Access Controller (DMA) Module
20.3.1.25 FTC Interrupt Mapping Register (FTCMAP)
Figure 20-43. FTC Interrupt Mapping Register (FTCMAP) [offset = B4h]
31 0
FTCAB[31:0]
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset
Table 20-33. FTC Interrupt Mapping Register (FTCMAP) Field Descriptions
Bit Field Value Description
31-0 FTCAB[n] Frame transfer complete (FTC) interrupt to Group A or Group B. Bit 0 corresponds to channel 0, bit 1
corresponds to channel 1, and so on.
0 FTC interrupt of the corresponding channel is routed to Group A.
1 FTC interrupt of the corresponding channel is routed to Group B.
20.3.1.26 LFS Interrupt Mapping Register (LFSMAP)
Figure 20-44. LFS Interrupt Mapping Register (LFSMAP) [offset = BCh]
31 0
LFSAB[31:0]
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset
Table 20-34. LFS Interrupt Mapping Register (LFSMAP) Field Descriptions
Bit Field Value Description
31-0 LFSAB[n] Last frame started (LFS) interrupt to Group A or Group B. Bit 0 corresponds to channel 0, bit 1
corresponds to channel 1, and so on.
0 LFS interrupt of the corresponding channel is routed to Group A.
1 LFS interrupt of the corresponding channel is routed to Group B.
20.3.1.27 HBC Interrupt Mapping Register (HBCMAP)
Figure 20-45. HBC Interrupt Mapping Register (HBCMAP) [offset = C4h]
31 0
HBCAB[31:0]
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset
Table 20-35. HBC Interrupt Mapping Register (HBCMAP) Field Descriptions
Bit Field Value Description
31-0 HBCAB[n] Half block complete (HBC) interrupt to Group A or Group B. Bit 0 corresponds to channel 0, bit 1
corresponds to channel 1, and so on.
0 HBC interrupt of the corresponding channel is routed to Group A.
1 HBC interrupt of the corresponding channel is routed to Group B.