www.ti.com
HTU Control Registers
1165
SPNU563A–March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
High-End Timer Transfer Unit (HTU) Module
24.4.20 Debug Control Register (HTU DCTRL)
This register allows to create watch points on access to a certain location. It is intended to help debug the
application execution during program development.
Figure 24-33. Debug Control Register (HTU DCTRL) [offset = 54h]
31 28 27 24 23 17 16
Reserved CPNUM Reserved HTUDBGS
R-0 R-0 R-0 R/W1CS-0
15 1 0
Reserved DBREN
R-0 R/WS-0
LEGEND: R/W = Read/Write; R = Read only; W1CS = Write 1 in suspend mode to clear the bit; WS = Write in suspend mode only; -n =
value after reset
Table 24-33. Debug Control Register (HTU DCTRL) Field Descriptions
Bit Field Value Description
31-28 Reserved 0 Reads return 0. Writes have no effect.
27-24 CPNUM CP Number. These bit fields indicate the CP that should cause the watch point to match.
0 CP A of DCP0
1h CP B of DCP0
2h CP A of DCP1
3h CP B of DCP1
4h CP A of DCP2
5h CP B of DCP2
6h CP A of DCP3
7h CP B of DCP3
8h CP A of DCP4
9h CP B of DCP4
Ah CP A of DCP5
Bh CP B of DCP5
Ch CP A of DCP6
Dh CP B of DCP6
Eh CP A of DCP7
Fh CP B of DCP7
23-17 Reserved 0 Reads return 0. Writes have no effect.
16 HTUDBGS HTU Debug Status. When the main memory address is equal to the unique address defined by WPR, or
lies in the specified range resulting from WMR, then the HTUDBGS is set. If in addition DBREN is set,
then the application code execution will be stopped.
A 1 must be written to this bit in order to clear it and to release the CPU from debug halting state.
0 Read: No watch point condition was detected.
Write: No effect.
1 Read: A watch point condition was detected.
Write: Clears the bit.
15-1 Reserved 0 Reads return 0. Writes have no effect.
0 DBREN Debug Request Enable
If a watch point matches and DBREN is set, then the application code execution will be stopped. This
bit can only be set or cleared when in debug mode. This bit and all other bits of the DCTRL, WPR and
WMR registers are reset by the test reset (nTRST) but not by the normal device reset.
To Next Page
Loading...
Need help?
General
