VIM Control Registers
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SPNU563A–March 2018
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Vectored Interrupt Manager (VIM) Module
19.9 VIM Control Registers
Table 19-5 lists the VIM module registers. Each register begins on a word boundary. All registers are 32-
bit, 16-bit, and 8-bit accessible for read and write. Write is only possible in privilege mode. The base
address of the control registers is FFFF FE00h. The base address of the ECC-related VIM registers is
FFFF FD00h. The address locations not listed are reserved.
Table 19-5. VIM Control Registers
Offset Acronym Register Description Section
ECC-related Registers
ECh ECCSTAT Interrupt Vector Table ECC Status Register Section 19.9.1
F0h ECCCTL Interrupt Vector Table ECC Control Register Section 19.9.2
F4h UERRADDR Uncorrectable Error Address Register Section 19.9.3
F8h FBVECADDR Fallback Vector Address Register Section 19.9.4
FCh SBERRADDR Single-Bit Error Address Register Section 19.9.5
Control Registers
00h IRQINDEX IRQ Index Offset Vector Register Section 19.9.7
04h FIQINDEX FIQ Index Offset Vector Register Section 19.9.8
10h FIRQPR0 FIQ/IRQ Program Control Register 0 Section 19.9.9
14h FIRQPR1 FIQ/IRQ Program Control Register 1 Section 19.9.9
18h FIRQPR2 FIQ/IRQ Program Control Register 2 Section 19.9.9
1Ch FIRQPR3 FIQ/IRQ Program Control Register 3 Section 19.9.9
20h INTREQ0 Pending Interrupt Read Location Register 0 Section 19.9.10
24h INTREQ1 Pending Interrupt Read Location Register 1 Section 19.9.10
28h INTREQ2 Pending Interrupt Read Location Register 2 Section 19.9.10
2Ch INTREQ3 Pending Interrupt Read Location Register 3 Section 19.9.10
30h REQENASET0 Interrupt Enable Set Register 0 Section 19.9.11
34h REQENASET1 Interrupt Enable Set Register 1 Section 19.9.11
38h REQENASET2 Interrupt Enable Set Register 2 Section 19.9.11
3Ch REQENASET3 Interrupt Enable Set Register 3 Section 19.9.11
40h REQENACLR0 Interrupt Enable Clear Register 0 Section 19.9.12
44h REQENACLR1 Interrupt Enable Clear Register 1 Section 19.9.12
48h REQENACLR2 Interrupt Enable Clear Register 2 Section 19.9.12
4Ch REQENACLR3 Interrupt Enable Clear Register 3 Section 19.9.12
50h WAKEENASET0 Wake-up Enable Set Register 0 Section 19.9.13
54h WAKEENASET1 Wake-up Enable Set Register 1 Section 19.9.13
58h WAKEENASET2 Wake-up Enable Set Register 2 Section 19.9.13
5Ch WAKEENASET3 Wake-up Enable Set Register 3 Section 19.9.13
60h WAKEENACLR0 Wake-up Enable Clear Register 0 Section 19.9.14
64h WAKEENACLR1 Wake-up Enable Clear Register 1 Section 19.9.14
68h WAKEENACLR2 Wake-up Enable Clear Register 2 Section 19.9.14
6Ch WAKEENACLR3 Wake-up Enable Clear Register 3 Section 19.9.14
70h IRQVECREG IRQ Interrupt Vector Register Section 19.9.15
74h FIQVECREG FIQ Interrupt Vector Register Section 19.9.16
78h CAPEVT Capture Event Register Section 19.9.17
80h-FCh CHANCTRL VIM Interrupt Control Register Section 19.9.18
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