Texas Instruments TMS570LC4357 User Manual

2
SPNU563A–March 2018
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Copyright © 2018, Texas Instruments Incorporated
Contents
Contents
Preface..................................................................................................................................... 104
1 Introduction ..................................................................................................................... 106
1.1 Designed for Safety Applications ....................................................................................... 107
1.2 Family Description ........................................................................................................ 108
1.3 Endianism Considerations............................................................................................... 111
1.3.1 TMS570: Big Endian (BE32) ................................................................................... 111
2 Architecture ..................................................................................................................... 112
2.1 Introduction ................................................................................................................ 113
2.1.1 Architecture Block Diagram .................................................................................... 113
2.1.2 Definitions of Terms ............................................................................................. 115
2.1.3 Bus Master / Slave Access Privileges ........................................................................ 118
2.1.4 CPU Interconnect Subsystem SDC MMR Port .............................................................. 118
2.1.5 Interconnect Subsystem Runtime Status..................................................................... 119
2.1.6 Master ID to PCRx............................................................................................... 119
2.2 Memory Organization .................................................................................................... 120
2.2.1 Memory-Map Overview ......................................................................................... 120
2.2.2 Memory-Map Table.............................................................................................. 122
2.2.3 Flash on Microcontrollers ....................................................................................... 129
2.2.4 On-Chip SRAM................................................................................................... 134
2.3 Exceptions ................................................................................................................. 139
2.3.1 Resets............................................................................................................. 139
2.3.2 Aborts ............................................................................................................. 139
2.3.3 System Software Interrupts..................................................................................... 141
2.4 Clocks ...................................................................................................................... 142
2.4.1 Clock Sources.................................................................................................... 142
2.4.2 Clock Domains ................................................................................................... 143
2.4.3 Low Power Modes............................................................................................... 145
2.4.4 Clock Test Mode................................................................................................. 146
2.4.5 Embedded Trace Macrocell (ETM-R5)........................................................................ 148
2.4.6 Safety Considerations for Clocks.............................................................................. 148
2.5 System and Peripheral Control Registers ............................................................................. 151
2.5.1 Primary System Control Registers (SYS) .................................................................... 151
2.5.2 Secondary System Control Registers (SYS2) ............................................................... 205
2.5.3 Peripheral Central Resource (PCR) Control Registers .................................................... 217
3 SCR Control Module (SCM)................................................................................................ 252
3.1 Overview ................................................................................................................... 253
3.1.1 Features........................................................................................................... 253
3.1.2 System Block Diagram.......................................................................................... 254
3.2 Module Operation......................................................................................................... 255
3.2.1 Block Diagram.................................................................................................... 255
3.2.2 Timeout Threshold Compare Block ........................................................................... 255
3.2.3 SCM Control Block .............................................................................................. 256
3.3 How to Use SCM ......................................................................................................... 257
3.3.1 How to Check the Parity Compare Logic..................................................................... 257
3.3.2 How to Initiate Self-test Sequence ............................................................................ 258

Texas Instruments TMS570LC4357 Specifications

General

Brand	Texas Instruments
Model	TMS570LC4357
Category	Microcontrollers
Language	English