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NMPU Registers
477
SPNU563A–March 2018
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System Memory Protection Unit (NMPU)
11.4.8 MPU Control Register 2 (MPUCTRL2)
Figure 11-11. MPU Control Register 2 (MPUCTRL2) [offset = 24h]
31 16
Reserved
R-0
15 4 3 0
Reserved ERRENA
R-0 R/WP-5h
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 11-11. MPU Control Register 2 (MPUCTRL2) Field Descriptions
Bit Field Value Description
31-4 Reserved 0 Reserved. Reads return 0.
3-0 ERRENA MPU Error Pulse Enable. This is the key for enabling ERROR pulse output generation for the
Error Signaling Module. This field is updated only if the write data is 5h or Ah. Register writes
are ignored for all other values of write data.
A built-in correction logic detects single bit soft error on this field and corrects the value in the
next cycle. Functionality and register read data remain the same during the correction cycle.
Read: Returns current value of ERRENA.
Write in Privilege:
5h Error pulse output to ESM is disabled.
Ah Error pulse output to ESM is enabled.
All other values Reserved. The bits remain unchanged.
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