PLL Control Registers
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SPNU563A–March 2018
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Oscillator and PLL
14.6 PLL Control Registers
The clock module has two registers (PLLCTL1 and PLLCTL2) located within the System and Peripheral
Control Registers, plus it has four bits located in other System and Peripheral Control Registers.
The FM-PLL is off at power-on. The clock source is enabled by clearing the appropriate bit in the Clock
Source Disable Register (CSDIS) or setting the appropriate bit in the Clock Source Disable Clear Register
(CSDISCLR) of the System and Peripheral Control Registers. [CSDISCLR and Clock Source Disable Set
Register (CSDISSET) also enable/disable the PLL and oscillator (and other clock sources).]
The LPOCLKDET module generates the OSCFAIL flag in the Global Status Register (GLBSTAT), of the
System and Peripheral Control Registers, if a problem with the reference oscillator is detected. The slip
signals are also registered in the RFSLIP and FBSLIP status flags in the Global Status Register
(GLBSTAT), of the System and Peripheral Control Registers, in order to indicate the source of a clock
failure.
The appropriate CLKSRnV bit for the PLL is set in the Clock Source Valid Status Register (CSVSTAT) of
the System and Peripheral Control Registers.
The following sections describe the two PLL registers used in the system module. These registers support
8-, 16-, and 32-bit write accesses. The reset values for these registers are configured so that an input
frequency in the range from 5 MHz to 20 MHz generates a valid clock.
Table 14-4. PLL Module Registers
Address Acronym Register Description Section
FFFF FF30h CSDIS Clock Source Disable Register Section 2.5.1.10
FFFF FF34h CSDISSET Clock Source Disable Set Register Section 2.5.1.11
FFFF FF38h CSDISCLR Clock Source Disable Clear Register Section 2.5.1.12
FFFF FF54h CSVSTAT Clock Source Valid Status Register Section 2.5.1.19
FFFF FF70h PLLCTL1 PLL Control 1 Register Section 2.5.1.25
FFFF FF74h PLLCTL2 PLL Control 2 Register Section 2.5.1.26
FFFF E100h PLLCTL3 PLL Control 3 Register Section 2.5.2.1
FFFF FFA0h GPREG1 General Purpose Register Section 2.5.1.34
FFFF FFECh GLBSTAT Global Status Register Section 2.5.1.48
FFFF E170h CLKSLIP Clock Slip Control Register Section 2.5.2.7
FFFF FF24h SSWPLL1 PLL Modulation Depth Measurement Control Register Section 14.6.1
FFFF FF28h SSWPLL2 SSW PLL BIST Control Register 2 Section 14.6.2
FFFF FF2Ch SSWPLL3 SSW PLL BIST Control Register 3 Section 14.6.3
Table 14-5. LPOCLKDET Module Registers
Address Acronym Register Description Section
FFFF FF88h LPOMONCTL LPO/CLock Monitor Control Register Section 2.5.1.31
FFFF FF8Ch CLKTEST Clock Test Register Section 2.5.1.31
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