Texas Instruments TMS570LC4357

ESM Control Registers www.ti.com
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SPNU563A–March 2018
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Error Signaling Module (ESM)
16.4.23 ESM Status Register 4 (ESMSR4)
This register is dedicated for Group1 Channel[63:32].
Figure 16-33. ESM Status Register 4 (ESMSR4) [offset = 58h]
31 16
ESF[63:48]
R/W1CP-X/0
15 0
ESF[47:32]
R/W1CP-X/0
LEGEND: R/W = Read/Write; W1CP = Write 1 to clear in privilege mode only; -n = value after reset/PORRST; X = value is unchanged
Table 16-25. ESM Status Register 4 (ESMSR4) Field Descriptions
Bit Field Value Description
63-32 ESF Error Status Flag. Provides status information on a pending error.
Read in User and Privileged mode. Write in Privileged mode only.
0 Read: No error occurred; no interrupt is pending.
Write: Leaves the bit unchanged.
1 Read: Error occurred; interrupt is pending.
Write: Clears the bit.
Note: After RST, if one of these flags are set and the corresponding interrupt are enabled, the
interrupt service routine will be called.