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ESM Control Registers
581
SPNU563A–March 2018
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Error Signaling Module (ESM)
16.4.28 ESM Interrupt Level Set/Status Register 7 (ESMILSR7)
This register is dedicated for Group1 Channel[95:64].
Figure 16-38. ESM Interrupt Level Set/Status Register 7 (ESMILSR7) [offset = 90h]
31 16
INTLVLSET[95:80]
R/WP-0
15 0
INTLVLSET[79:64]
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 16-30. ESM Interrupt Level Set/Status Register 7 (ESMILSR7) Field Descriptions
Bit Field Value Description
95-64 INTLVLSET Set interrupt level.
Read in User and Privileged mode. Write in Privileged mode only.
0 Read: Read: Interrupt of channel x is mapped to low-level interrupt line.
Write: Leaves the bit and the corresponding clear bit in the ESMILCR7 register unchanged.
1 Read: Interrupt of channel x is mapped to high-level interrupt line.
Write: Maps interrupt of channel x to high-level interrupt line and sets the corresponding clear bit in
the ESMILCR7 register.
16.4.29 ESM Interrupt Level Clear/Status Register 7 (ESMILCR7)
This register is dedicated for Group1 Channel[95:64].
Figure 16-39. ESM Interrupt Level Clear/Status Register 7 (ESMILCR7) [offset = 94h]
31 16
INTLVLCLR[95:80]
R/WP-0
15 0
INTLVLCLR[79:64]
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 16-31. ESM Interrupt Level Clear/Status Register 7 (ESMILCR7) Field Descriptions
Bit Field Value Description
95-64 INTLVLCLR Clear interrupt level.
Read in User and Privileged mode. Write in Privileged mode only.
0 Read: Interrupt of channel x is mapped to low-level interrupt line.
Write: Leaves the bit and the corresponding set bit in the ESMILSR7 register unchanged.
1 Read: Interrupt of channel x is mapped to high-level interrupt line.
Write: Maps interrupt of channel x to low-level interrupt line and clears the corresponding set bit in
the ESMILSR7 register.