DCAN Control Registers
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SPNU563A–March 2018
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Controller Area Network (DCAN) Module
27.17.15 Transmission Request Registers (DCAN TXRQ12 to DCAN TXRQ78)
These registers hold the TxRqst bits of the implemented message objects. By reading out these bits, the
CPU can check for pending transmission requests. The TxRqst bit in a specific message object can be
set/reset by the CPU via the IF1/IF2 Message Interface Registers, or by the Message Handler after
reception of a remote frame or after a successful transmission.
Figure 27-34. Transmission Request 12 Register (DCAN TXRQ12) [offset = 88h]
31 0
TxRqst[32:1]
R-0
LEGEND: R = Read only; -n = value after reset
Figure 27-35. Transmission Request 34 Register (DCAN TXRQ34) [offset = 8Ch]
31 0
TxRqst[64:33]
R-0
LEGEND: R = Read only; -n = value after reset
Figure 27-36. Transmission Request 56 Register (DCAN TXRQ56) [offset = 90h]
31 0
TxRqst[96:65]
R-0
LEGEND: R = Read only; -n = value after reset
Figure 27-37. Transmission Request 78 Register (DCAN TXRQ78) [offset = 94h]
31 0
TxRqst[128:97]
R-0
LEGEND: R = Read only; -n = value after reset
Table 27-20. Transmission Request Registers Field Descriptions
Bit Name Value Description
31-0 TxRqst[128:1] Transmission Request Bits (for all message objects).
0 No transmission has been requested for this message object.
1 The transmission of this message object is requested and is not yet done.
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