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Double Control Packet Configuration Memory
1177
SPNU563A–March 2018
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High-End Timer Transfer Unit (HTU) Module
Table 24-45. Initial N2HET Address and Control Register (HTU IHADDRCT) Field Descriptions (continued)
Bit Field Value Description
15-13 Reserved 0 Reads return 0. Writes have no effect.
12-2 IHADDR Initial N2HET Address
The initial N2HET Address points to the N2HET field, which is the first element of the frame. The
N2HET address (bits 12:2) increments by 1 for each 32-bit N2HET field and starts with 0 at the first 32-
bit field in the N2HET RAM.
Note: When the HTU addresses the N2HET RAM it uses only the number of address bits required for
the actual N2HET RAM size. If the N2HET address exceeds the actual N2HET RAM size, the unused
MSB bits of the address will be ignored and the address rolls over to the start of the N2HET RAM.
1-0 Reserved 0 Reads return 0. Writes have no effect.
24.5.4 Initial Transfer Count Register (HTU ITCOUNT)
Figure 24-45. Initial Transfer Count Register (HTU ITCOUNT)
31 21 20 16
Reserved IETCOUNT
R-0 R/WP-X
15 8 7 0
Reserved IFTCOUNT
R-0 R/WP-X
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset; X = Unknown
Table 24-46. Initial Transfer Count Register (HTU ITCOUNT) Field Descriptions
Bit Field Value Description
31-21 Reserved 0 Reads return 0. Writes have no effect.
20-16 IETCOUNT Initial Element Transfer Count
Defines the number of element transfers.
15-8 Reserved 0 Reads return 0. Writes have no effect.
7-0 IFTCOUNT Initial Frame Transfer Count
Defines the number of frame transfers.
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