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ESM Control Registers
579
SPNU563A–March 2018
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Error Signaling Module (ESM)
16.4.24 ESM Influence ERROR Pin Set/Status Register 7 (ESMIEPSR7)
This register is dedicated for Group1 Channel[95:64].
Figure 16-34. ESM Influence ERROR Pin Set/Status Register 7 (ESMIEPSR7) [offset = 80h]
31 16
IEPSET[95:80]
R/WP-0
15 0
IEPSET[79:64]
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 16-26. ESM Influence ERROR Pin Set/Status Register 7 (ESMIEPSR7) Field Descriptions
Bit Field Value Description
95-64 IEPSET Set influence on ERROR pin.
Read in User and Privileged mode. Write in Privileged mode only.
0 Read: Failure on channel x has no influence on ERROR pin.
Write: Leaves the bit and the corresponding clear bit in the ESMIEPCR7 register unchanged.
1 Read: Failure on channel x has influence on ERROR pin.
Write: Enables failure influence on ERROR pin and sets the corresponding clear bit in the
ESMIEPCR7 register.
16.4.25 ESM Influence ERROR Pin Clear/Status Register 7 (ESMIEPCR7)
This register is dedicated for Group1 Channel[95:64].
Figure 16-35. ESM Influence ERROR Pin Clear/Status Register 7 (ESMIEPCR7) [offset = 84h]
31 16
IEPCLR[95:80]
R/WP-0
15 0
IEPCLR[79:64]
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 16-27. ESM Influence ERROR Pin Clear/Status Register 7 (ESMIEPCR7) Field Descriptions
Bit Field Value Description
95-64 IEPCLR Clear influence on ERROR pin.
Read in User and Privileged mode. Write in Privileged mode only.
0 Read: Failure on channel x has no influence on ERROR pin.
Write: Leaves the bit and the corresponding clear bit in the ESMIEPSR7 register unchanged.
1 Read: Failure on channel x has influence on ERROR pin.
Write: Disables failure influence on ERROR pin and clears the corresponding clear bit in the
ESMIEPSR7 register.
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