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STC Control Registers
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SPNU563A–March 2018
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Self-Test Controller (STC) Module
10.8.3 Self-Test Run Timeout Counter Preload Register (STCTPR)
This register is described in Figure 10-10 and Table 10-11.
NOTE: On a power-on reset or system reset, this register gets reset to its default values.
Figure 10-10. Self-Test Run Timeout Counter Preload Register (STCTPR) [offset = 08h]
31 0
RTOD
R/WP-FFFF FFFFh
LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after nPORST (power on reset) or System reset
Table 10-11. Self-Test Run Timeout Counter Preload Register (STCTPR)
Bit Field Description
31-0 RTOD Self-test timeout count preload.
This register contains the total number of VBUS clock cycles it will take before an self-test timeout error
(TO_ERR) will be triggered after the initiation of the self-test run. This is a fail safe feature to prevent the device
from hanging up due to a run away test during the self-test.
The preload count value gets loaded into the self-test time out down counter whenever a self-test run is
initiated (STC_KEY is enabled) and gets disabled on completion of a self-test run.
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