Texas Instruments TMS570LC4357 User Manual

HTU Control Registers www.ti.com
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SPNU563A–March 2018
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High-End Timer Transfer Unit (HTU) Module
24.4.9 Buffer Full Interrupt Enable Set Register (HTU BFINTS)
This registers allows to enable the buffer full interrupts for the different control packets. Reading registers
BFINTS and BFINTC will return the same bits indicating the status which interrupt is enabled (1) or
disabled (0).
Figure 24-22. Buffer Full Interrupt Enable Set Register (HTU BFINTS) [offset = 24h]
31 16
Reserved
R-0
15 0
BFINTENA
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 24-21. Buffer Full Interrupt Enable Set Register (HTU BFINTS) Field Descriptions
Bit Field Value Description
31-16 Reserved 0 Reads return 0. Writes have no effect.
15-0 BFINTENA Bus Full Interrupt Enable Bits. If the interrupt for CP A of a DCP is enabled, then the interrupt is
generated once buffer A is full, that is, once the frame counter CFTCTA decrements to 0. The same
applies for CP B (and CFTCTB).
0 Interrupt is disabled. Writing a 0 has no effect.
1 Writing to bit (2*x) enables the interrupt for CP A of DCP x.
Writing to bit (2*x+1) enables the interrupt for CP B of DCP x.
24.4.10 Buffer Full Interrupt Enable Clear Register (HTU BFINTC)
This registers allows to disable the buffer full interrupts for the different control packets. Reading registers
BFINTS and BFINTC will return the same bits indicating the status which interrupt is enabled (1) or
disabled (0)
Figure 24-23. Buffer Full Interrupt Enable Clear Register (HTU BFINTC) [offset = 28h]
31 16
Reserved
R-0
15 0
BFINTDIS
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 24-22. Buffer Full Interrupt Enable Clear Register (HTU BFINTC) Field Descriptions
Bit Field Value Description
31-16 Reserved 0 Reads return 0. Writes have no effect.
15-0 BFINTDIS Buffer Full Interrupt Disable Bits
0 Interrupt is disabled. Writing a 0 has no effect.
1 Writing to bit (2*x) disables the interrupt for CP A of DCP x.
Writing to bit (2*x+1) disables the interrupt for CP B of DCP x.

Texas Instruments TMS570LC4357 Specifications

General

Brand	Texas Instruments
Model	TMS570LC4357
Category	Microcontrollers
Language	English