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STC1 Segment 0 (CPU) Test Coverage and Duration
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SPNU563A–March 2018
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Self-Test Controller (STC) Module
10.5 STC1 Segment 0 (CPU) Test Coverage and Duration
The test coverage and number of test execution cycles (STCCLK) for each test interval are shown in
Table 10-2.
Table 10-2. STC1 Segment 0 Test Coverage and Duration
Intervals Test Coverage (%) Test Time (Cycles)
0 0 0
1 56.85 1629
2 64.19 3258
3 68.76 4887
4 71.99 6516
5 75.00 8145
6 76.61 9774
7 78.08 11403
8 79.20 13032
9 80.18 14661
10 81.03 16290
11 81.90 17919
12 82.58 19548
13 83.24 21177
14 83.73 22806
15 84.15 24435
16 84.52 26064
17 84.90 27693
18 85.26 29322
19 85.68 30951
20 86.05 32580
21 86.40 34209
22 86.68 35838
23 86.94 37467
24 87.21 39096
25 87.48 40725
26 87.74 42354
27 87.98 43983
28 88.18 45612
29 88.38 47241
30 88.56 48870
31 88.75 50499
32 88.93 52128
33 89.10 53757
34 89.23 55386
35 89.41 57015
36 89.55 58644
37 89.70 60273
38 89.83 61902
39 89.96 63531
40 90.10 65160
41 90.23 66789
42 90.33 68418
43 90.43 70047
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