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CRC Control Registers
661
SPNU563A–March 2018
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Cyclic Redundancy Check (CRC) Controller Module
18.4.33 Channel 2 Raw Data Low Register (RAW_DATAREGL2)
Figure 18-41. Channel 2 Raw Data Low Register (RAW_DATAREGL2) [offset = B8h]
31 0
RAW_DATA2
R-0
LEGEND: R = Read only; -n = value after reset
Table 18-37. Channel 2 Raw Data Low Register (RAW_DATAREGL2) Field Descriptions
Bit Field Description
31-0 RAW_DATA2 Channel 2 Raw Data Low Register. This register contains bits 31:0 of the uncompressed raw data..
18.4.34 Channel 2 Raw Data High Register (RAW_DATAREGH2)
Figure 18-42. Channel 2 Raw Data High Register (RAW_DATAREGH2) [offset = BCh]
31 0
RAW_DATA2
R-0
LEGEND: R = Read only; -n = value after reset
Table 18-38. Channel 2 Raw Data High Register (RAW_DATAREGH2) Field Descriptions
Bit Field Description
31-0 RAW_DATA2 Channel 2 Raw Data High Register. This register contains bits 63:32 of the uncompressed raw data..