PLL
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SPNU563A–March 2018
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Oscillator and PLL
14.5.4 Recovery from a PLL Failure
If PLL1 fails, the PLL’s slip causes the valid flag to be locked and causes the clock source into GCM clock
source 1 to shift from the PLL to the oscillator. The RFSLIP or FBSLIP status flags in the Global Status
Register (GLBSTAT) of the System and Peripheral Control Registers are also set. PLL1 may be re-
enabled (though if the failure was caused by a hard-fault, the re-enable will fail) through the following
procedure:
1. Switch all clock domains from PLL1 to the oscillator (for example, GHVSRC uses oscillator, VCLKAn
uses oscillator or VCLK, and so on).
2. Disable PLL1 by setting the appropriate bit in the Clock Source Disable Set Register (CSDISSET) of
the System and Peripheral Control Registers. This action disables the PLL and causes the slip signal
to no longer be driven. Valid is not released until the slip is cleared.
3. Clear the RFSLIP or FBSLIP status flags in the Global Status Register (GLBSTAT) of the System and
Peripheral Control Registers by writing a 1 to the bit. After this step, the valid flag is unlocked and
cleared if it was previously set.
4. Re-enable PLL1 by setting the appropriate bit in the Clock Source Disable Clear Register
(CSDISCLR).
5. Switch the clock domains back to PLL1.
If PLL2 fails, the PLL’s slip causes the valid flag to be locked. There is no autonomous change of clock
source for PLL2. Neither the RFSLIP or FBSLIP status flags in the Global Status Register (GLBSTAT) of
the System and Peripheral Control Registers are set. PLL2 may be re-enabled in a similar procedure to
re-enabling PLL1 (though if the failure was caused by a hard-fault, the re-enable will fail):
1. Switch all clock domains from PLL2 to the oscillator (for example, GHVSRC uses oscillator, VCLKAn
uses oscillator or VCLK, and so on).
2. Disable PLL2 by setting the appropriate bit in the Clock Source Disable Set Register (CSDISSET) of
the System and Peripheral Control Registers. This action disables the PLL and causes the slip signal
to no longer be driven. Valid is not released until the slip is cleared.
3. Reset PLL2 Valid by writing a 1 to both RFSLIP and FBSLIP status flags in the Global Status Register
(GLBSTAT) of the System and Peripheral Control Registers (even though they are not set by the slip).
After this step, the valid flag is unlocked and cleared if it was previously set.
4. Re-enable PLL2 by setting the appropriate bit in the Clock Source Disable Clear Register
(CSDISCLR).
5. Switch the clock domains back to PLL2.
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