Device Modes of Operation
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SPNU563A–March 2018
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General-Purpose Input/Output (GIO) Module
25.4 Device Modes of Operation
The GIO module behaves differently in different modes of operation. There are two main modes:
• Emulation mode
• Power-down mode (low-power mode)
25.4.1 Emulation Mode
Emulation mode is used by debugger tools to stop the CPU at breakpoints to read registers.
NOTE: Emulation Mode and Emulation Registers
Emulation mode is a mode of operation of the device and is separate from the GIO
emulation registers (GIOEMU1 and GIOEMU2). The contents of these emulation registers
are identical to the contents of GIO offset registers (GIOOFF1 and GIOOFF2). Both
emulation registers and GIO offset registers are NOT cleared when they are read in
emulation mode. GIO offset registers are cleared when they are read in normal mode (other
than emulation mode). The emulation registers are NOT cleared when they are read in
normal mode. The intention for the emulation registers is that software can use them without
clearing the flags.
During emulation mode:
• External interrupts are not captured because the VIM is unable to service interrupts.
• Any register can be read without affecting the state of the system.
• A write to a register still does affect the state of the system.
25.4.2 Power-Down Mode (Low-Power Mode)
In power-down mode, the clock signal to the GIO module is disabled. Thus, there is no switching and the
only current draw comes from leakage current. In power-down mode, interrupt pins become level-sensitive
rather than edge-sensitive. The polarity bit changes function from falling-edge-triggered to low-level-
triggered and rising-edge-triggered to high-level-triggered. A corresponding level on an interrupt pin pulls
the module out of low-power mode, if the interrupt is also enabled to wake up the device out of a low-
power mode.
25.4.2.1 Module-Level Power Down
The GIO module can be placed into a power down state by disabling the GIO peripheral module via the
appropriate bit in the peripheral power down register. Please refer to the Peripheral Central Resource
Registers (Section 2.5.3) for details.
25.4.2.2 Device-Level Power Down
The entire device can be placed in one of the pre-defined low-power modes: doze, snooze, or sleep using
the clock source and clock domain disable registers in the system module.
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