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Exceptions
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SPNU563A–March 2018
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Architecture
2.3.2.5 Conditions That Generate Aborts
An Abort is generated under the following conditions on the TMS570LC43x microcontrollers.
• Access to an illegal address (a non-implemented address)
• Access to a protected address (protection violation)
• Parity / ECC / Time-out Error on a valid access
Illegal Addresses:
The illegal addresses and the responses to an access to these addresses are defined in Table 2-2.
Addresses Protected By MPU:
For more details on the MPU configuration, refer to the ARM
®
Cortex
®
-R5F Technical Reference Manual.
A memory access violation is logged as a permission fault in the CPU’s fault status register and the virtual
address of the access is logged into the CPU’s fault address register.
Protection of Peripheral Register and Memory Frames:
Accesses to the peripheral register and memory frames can be protected either by configuring the MPU or
by configuring the Peripheral Central Resource (PCR) controller registers.
The PCR module PPROTSETx registers contain one bit per peripheral select quadrant. These bits define
the access permissions to the peripheral register frames. If the CPU attempts to write to a peripheral
register for which it does not have the correct permissions, a protection violation is detected and an Abort
occurs.
Some modules also enforce register updates to only be allowed when the CPU is in a privileged mode of
operation. If the CPU writes to these registers in user mode, the writes are ignored.
The PCR module PMPROTSETx registers contain one bit per peripheral memory frame. These bits define
the access permissions to the peripheral memory frames. If the CPU attempts to write to a peripheral
memory for which it does not have the correct permissions, a protection violation is detected and an Abort
occurs.
NOTE: No Access Protection for Reads
The PCR PPROTSETx and PMPROTSETx registers protect the peripheral registers and
memories against illegal writes by the CPU. The CPU can read from the peripheral registers
and memories in both user and privileged modes.
2.3.3 System Software Interrupts
The system module provides the capability of generating up to four software interrupts. A software
interrupt is generated by writing the correct key value to either of the four System Software Interrupt
Registers (SSIRx). The SSI registers also allow the application to provide a label for that software
interrupt. This label is an 8-bit value that can then be used by the interrupt service routine to perform the
required task based on the value provided. The source of the system software interrupt is reflected in the
system software interrupt vector (SSIVEC) register. The pending interrupt flag is captured in SSIF register.
NOTE: The SSIRx, SSIVEC and SSIF registers are banked registers. This allows the system
module to support up to two CPUs for system software interrupt generation. Each CPU will
have its own banked SSI registers. Both CPUs will see the SSI registers at the same
address. The system module decodes the unique master ID corresponding to the CPU's
access to the banked registers.
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