SCM Registers
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SPNU563A–March 2018
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SCR Control Module (SCM)
3.4 SCM Registers
The SCM registers are listed in Table 3-1 . Each register begins on a word boundary. The registers
support 8-, 16-, and 32-bit accesses. The address offset is specified from the base address of
FFFF 0A00h.
Registers are accessed through a dedicated MMR interface. Support only read, write, and write non-
posted. Read and write are always returning response status. A write to reserved bits has no effect.
If there is soft error or any other event that results in an unsupported command such as readlink-write
conditional or broadcast bus transactions, the MMR interface will return with response bus error for
unsupported command. Software should check for valid address and whether the target is in low power
mode or not prior to issue a retry access.
Table 3-1. SCM Registers
Offset Acronym Register Description Section
00h SCMREVID SCM REVID Register Section 3.4.1
04h SCMCNTRL SCM Control Register Section 3.4.2
08h SCMTHRESHOLD SCM Compare Threshold Counter Register Section 3.4.3
10h SCMIAERR0STAT SCM Initiator Error0 Status Register Section 3.4.4
14h SCMIAERR1STAT SCM Initiator Error1 Status Register Section 3.4.5
18h SCMIASTAT SCM Initiator Active Status Register Section 3.4.6
20h SCMTASTAT SCM Target Active Status Register Section 3.4.7
3.4.1 SCM REVID Register (SCMREVID)
Figure 3-5. SCM REVID Register (SCMREVID) [offset = 00h]
31 30 29 28 27 16
SCHEME Reserved FUNC
R-1 R-0 R-A0Bh
15 11 10 8 7 6 5 0
RTL MAJOR CUSTOM MINOR
R-0 R-0 R-0 R-2h
LEGEND: R = Read only; -n = value after synchronous reset on system reset
Table 3-2. SCM REVID Register (SCMREVID) Field Descriptions
Bit Field Value Description
31-30 SCHEME 1 Identification scheme.
29-28 Reserved 0 Reserved. Reads return 0.
27-16 FUNC A0Bh Indicates functionally equivalent module family.
15-11 RTL 0 RTL version number.
10-8 MAJOR 0 Major revision number.
7-6 CUSTOM 0 Indicates device-specific implementation.
5-0 MINOR 2h Minor revision number.
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