Texas Instruments TMS570LC4357 User Manual

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SPNU563A–March 2018
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Interconnect
4.4.4 Error Unexpected Transaction Register (ERR_UNEXPECTED_TRANS)
Figure 4-5. Error Unexpected Transaction Register (ERR_UNEXPECTED_TRANS) (offset = 0Ch)
31 16
Reserved
R-0
15 6 5 0
Reserved ERR_UNEXPECTED_TRANS
R-0 R-0
LEGEND: R = Read only; -n = value after reset
Table 4-9. Error Unexpected Transaction Register (ERR_UNEXPECTED_TRANS) Field Descriptions
Bit Field Value Description
31-6 Reserved 0 Reads return 0 and writes have no effect.
5-0 ERR_UNEXPECTED_TRANS Error related to unexpected transaction sent by the master. When set, each bit
indicates the transaction processing block inside the interconnect corresponding to
the master is detected by the interconnect checker to have a fault.
bit 0: PS_SCR_M master
bit 1: POM master
bit 2: DMA PortA master
bit 3: Reserved
bit 4: Cortex-R5F CPU master.
bit 5: ACP-M master
4.4.5 Error Transaction ID Register (ERR_TRANS_ID)
Figure 4-6. Error Transaction ID Register (ERR_TRANS_ID) (offset = 10h)
31 16
Reserved
R-0
15 6 5 0
Reserved ERR_TRANS_ID
R-0 R-0
LEGEND: R = Read only; -n = value after reset
Table 4-10. Error Transaction ID Register (ERR_TRANS_ID) Field Descriptions
Bit Field Value Description
31-6 Reserved 0 Reads return 0 and writes have no effect.
5-0 ERR_TRANS_ID Error related to mismatch on the transaction ID. When set, each bit indicates the transaction
processing block inside the interconnect corresponding to the master is detected by the
interconnect checker to have a fault.
bit 0: PS_SCR_M master
bit 1: POM master
bit 2: DMA PortA master
bit 3: Reserved
bit 4: Cortex-R5F CPU master.
bit 5: ACP-M master

Texas Instruments TMS570LC4357 Specifications

General

Brand	Texas Instruments
Model	TMS570LC4357
Category	Microcontrollers
Language	English