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Flash Control Registers
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SPNU563A–March 2018
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Copyright © 2018, Texas Instruments Incorporated
F021 Level 2 Flash Module Controller (L2FMC)
7.10 Flash Control Registers
This section details the Flash module registers, summarized in Table 7-12. The Flash module control
registers can only be read and/or written by the CPU while in privileged mode. Each register begins on a
word boundary. All registers are 32-bit, 16-bit and 8-bit accessible. The start address of the Flash module
is FFF8 7000h.
Table 7-12. Flash Control Registers
Offset Acronym Register Description Section
00h FRDCNTL Flash Read Control Register Section 7.10.1
04h FSPRD Read Margin Control Register Section 7.10.2
08h EE_FEDACCTRL1 EEPROM Error Correction Control Register 1 Section 7.10.3
14h FEDAC_PASTATUS Flash Port A Error and Status Register Section 7.10.4
18h FEDAC_PBSTATUS Flash Port B Error and Status Register Section 7.10.5
1Ch FEDAC_GBLSTATUS Flash Global Error and Status Register Section 7.10.6
24h FEDACSDIS Flash Error Detection and Correction Sector Disable
Register
Section 7.10.7
28h FPRIM_ADD_TAG Flash Primary Address Tag Register Section 7.10.8
2Ch FDUP_ADD_TAG Flash Duplicate Address Tag Register Section 7.10.9
30h FBPROT Flash Bank Protection Register Section 7.10.10
34h FBSE Flash Bank Sector Enable Register Section 7.10.11
38h FBBUSY Flash Bank Busy Register Section 7.10.12
3Ch FBAC Flash Bank Access Control Register Section 7.10.13
40h FBPWRMODE Flash Bank Power Mode Register Section 7.10.14
44h FBPRDY Bank/Pump Ready Register Section 7.10.15
48h FPAC1 Flash Pump Access Control Register 1 Section 7.10.16
50h FMAC Flash Module Access Control Register Section 7.10.17
54h FMSTAT Flash Module Status Register Section 7.10.18
58h FEMU_DMSW EEPROM Emulation Data MSW Register Section 7.10.19
5Ch FEMU_DLSW EEPROM Emulation Data LSW Register Section 7.10.20
60h FEMU_ECC EEPROM Emulation Address Register Section 7.10.21
64h FLOCK Flash Lock Register Section 7.10.22
6Ch FDIAGCTRL Diagnostic Control Register Section 7.10.23
74h FRAW_ADDR Raw Address Section 7.10.24
7Ch FPAR_OVR Parity Override Register Section 7.10.25
B4h RCR_VALID Reset Configuration Valid Register Section 7.10.26
B8h ACC_THRESHOLD Crossbar Access Time Threshold Register Section 7.10.27
C0h FEDACSDIS2 Flash Error Detection and Correction Sector Disable
Register 2
Section 7.10.28
D0h RCR_VALUE0 Lower Word of the Reset Configuration Read Register Section 7.10.29
D4h RCR_VALUE1 Upper Word of the Reset Configuration Read Register Section 7.10.30
288h FSM_WR_ENA FSM Register Write Enable Register Section 7.10.31
2B8h EEPROM_CONFIG EEPROM Emulation Configuration Register Section 7.10.32
2C0h FSM_SECTOR1 FSM Sector Register 1 Section 7.10.33
2C4h FSM_SECTOR2 FSM Sector Register 2 Section 7.10.34
400h FCFG_BANK Flash Bank Configuration Register Section 7.10.35
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