PLL Control Registers
www.ti.com
536
SPNU563A–March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Oscillator and PLL
Table 14-6. SSW PLL BIST Control Register 1 (SSWPLL1) Field Descriptions (continued)
Bit Field Value Description
3-1 TAP_COUNTER_DIS The value in this register is used to program a particular bit in CLKOUT counter.
When that particular bit in CLKOUT counter becomes 1, then both the CLKOUT
counter and the CAPTURE counter will stop counting when EXT_COUNTER_EN = 0.
When EXT_COUNTER_EN = 1, this bit field is not used.
0 Bit 16 of CLKOUT counter is selected. When this bit is set and the modulation period
finishes, the counters are disabled and READ_READY_FLAG is set.
1h Bit 18 of CLKOUT counter is selected.
2h Bit 20 of CLKOUT counter is selected.
3h Bit 22 of CLKOUT counter is selected.
4h Bit 24 of CLKOUT counter is selected.
5h Bit 26 of CLKOUT counter is selected.
6h Bit 28 of CLKOUT counter is selected.
7h Bit 30 of CLKOUT counter is selected.
0 EXT_COUNTER_EN Measurement mode.
0 Modulation Depth Measurement mode.
1 Frequency Measurement mode.
14.6.2 SSW PLL BIST Control Register 2 (SSWPLL2)
This is an observation register used to log counter value for the capture counter inside the PLL wrapper.
The SSWPLL2 register is shown in Figure 14-7 and described in Table 14-7. This register applies to PLL1,
but does not apply to PLL2.
Figure 14-7. SSW PLL BIST Control Register 2 (SSWPLL2) [offset = 28h]
31 16
SSW_CAPTURE_COUNT
R-0
15 0
SSW_CAPTURE_COUNT
R-0
LEGEND: R = Read only; -n = value after reset
Table 14-7. SSW PLL BIST Control Register 2 (SSWPLL2) Field Descriptions
Bit Field Description
31-0 SSW_CAPTURE_COUNT Capture count. This register returns the value of the capture count.
When EXT_COUNTER_EN = 0, this counter increments within a fixed modulation window.
When EXT_COUNTER_EN = 1, this counter increments based upon the oscillator.
To Next Page
Loading...
Need help?
General
