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EMIF Module Architecture
797
SPNU563A–March 2018
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Copyright © 2018, Texas Instruments Incorporated
External Memory Interface (EMIF)
Table 21-1. EMIF Pins Used to Access Both SDRAM and Asynchronous Memories (continued)
Pins(s) I/O Description
EMIF_nWE O Active-low write enable.
When interfacing to SDRAM, this pin is connected to the nWE pin of the SDRAM and is used to
send commands to the device.
When interfacing to an asynchronous device, this pin provides a signal which is active-low during
the strobe period of an asynchronous write access cycle.
Table 21-2. EMIF Pins Specific to SDRAM
Pin(s) I/O Description
EMIF_nCS[0] O Active-low chip enable pin for SDRAM devices.
This pin is connected to the chip-select pin of the attached SDRAM device and is used for
enabling/disabling commands. By default, the EMIF keeps this SDRAM chip select active, even if
the EMIF is not interfaced with an SDRAM device. This pin is deactivated when accessing the
asynchronous memory bank and is reactivated on completion of the asynchronous access.
EMIF_nRAS O Active-low row address strobe pin.
This pin is connected to the nRAS pin of the attached SDRAM device and is used for sending
commands to the device.
EMIF_nCAS O Active-low column address strobe pin.
This pin is connected to the nCAS pin of the attached SDRAM device and is used for sending
commands to the device.
EMIF_CKE O Clock enable pin.
This pin is connected to the CKE pin of the attached SDRAM device and is used for issuing the
SELF REFRESH command which places the device in self refresh mode. See Section 21.2.5.7
for details.
EMIF_CLK O SDRAM clock pin.
This pin is connected to the CLK pin of the attached SDRAM device. See Section 21.2.1 for
details on the clock signal.
Table 21-3. EMIF Pins Specific to Asynchronous Memory
Pin(s) I/O Description
EMIF_nCS[4:2] O Active-low chip enable pins for asynchronous devices.
These pins are meant to be connected to the chip-select pins of the attached asynchronous
device. These pins are active only during accesses to the asynchronous memory.
EMIF_nWAIT I Wait input with programmable polarity.
A connected asynchronous device can extend the strobe period of an access cycle by asserting
the EMIF_nWAIT input to the EMIF as described in Section 21.2.6.6. To enable this functionality,
the EW bit in the asynchronous 1 configuration register (CE2CFG) must be set to 1. In addition,
the WP0 bit in CE2CFG must be configured to define the polarity of the EMIF_nWAIT pin.
EMIF_nOE O Active-low pin enable for asynchronous devices.
This pin provides a signal which is active-low during the strobe period of an asynchronous read
access cycle.
21.2.4 EMIF Signal Multiplexing Control
Several EMIF signals are multiplexed with other functions on this microcontroller. Please refer to the I/O
Multiplexing Module chapter of the technical reference manual for more information on how to enable the
output of these EMIF signals.
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